The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. In at least some examples, FinFET fabrication may include epitaxial growth of source and drain regions in each of a p-type FinFET and an n-type FinFET, for example, by way of a dual-epi process. However, conventional dual-epi processes are limited inasmuch as contact resistivity and contact area (e.g., silicide contact area) cannot be improved (e.g., increased) due to pitch scaling, without a trade-off in capacitance, and the choice of materials is limited by the high thermal budget of front-end-of-line (FEOL) processes. The possibility to improve source/drain stressors (e.g., stress applied to a device channel) is also limited for similar reasons. Moreover, there is a stress reduction that occurs due to the conventional pre-amorphization implant (PAI) process (e.g., used in conjunction with silicide formation). Thus, existing techniques have not proved entirely satisfactory in all respects.